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|Title:||Design and Implementation of Area Efficient Ketje Processor|
|Authors:||Singh, A. K.|
|Abstract:||In this thesis, implementation of an authenticated encryption function Ketje is presented. It is built on a one-stage pipelined architecture of the low area co-processor of Keccak. The core utilizes a multi read port to read data from memory. The rho operation was performed by using a barrel rotator. Pipelining of the architecture was done to improve performance. The proposed core is implemented in commercially available Xilinx FPGA chips. It is observed that for the proposed architecture, the dynamic power consumed for the maximum clock frequency 243.748 MHz is 0.389W. Comparison with reference [2, 3] shows that the processor has better performance in terms of area-delay product. Further, ASIC synthesis of this design i.e. Ketje processor is performed using Synopsys Design Compiler and commercially available 90nm standard CMOS technology library.|
|Appears in Collections:||03. EE|
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