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|Title:||Design and Implementaion of 32-bit Risc Processor|
|Authors:||Singh, M. K.|
|Abstract:||RISC is a design strategy to implement instruction set architecture based on a fixed instruction size which reduces the hardware complexity, execution time, cost and other parameters taken into account during theimplementation of the design. In this thesis, the author presented a 32-bit non-pipelined RISC processor. The processor implements the Harvard memory architecture, so the instruction and data memory spaces are both physically and logically separate. The processor consists of the blocks, namely, program counter, controller, ALU, instruction memory and data memory. The processor has been designed for executing 16-instruction set. The design of the processor is coded using Verilog HDL and synthesized using XST tool, targeting a commercially available FPGA device XA3S500E-4CPG132. The maximum frequency of this design is 450.958MHz. Further, the ASIC implementation of the processor is done using Synopsys tool.|
|Appears in Collections:||03. EE|
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